This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-274504, filed on Sep. 11, 2001; the entire contents of which are incorporated herein by reference.
This invention relates to a semiconductor device. More particularly, it relates to a semiconductor device having a package structure of a surface-mounting type and especially suitable for carrying so-called power semiconductors such as power transistors and rectifier elements, for example.
Surface-mounting semiconductor devices have various advantages. One of the advantages is reliable, easy mounting on a mounting substrate having formed an electrode pattern by a process such as solder reflow technique or solder flow technique. Others are compactness, light weight, high reliability, and so on.
FIG. 11 is a schematic diagram showing a cross-sectional structure of a conventional surface-mounting semiconductor device of a resin-molded type.
FIG. 12 is a schematic diagram of the semiconductor device, viewed from its bottom.
The semiconductor device shown in FIGS. 11 and 12 has a package structure often called xe2x80x9cflat packagexe2x80x9d. A first lead frame 104 is connected on the upper surface of a semiconductor chip 102 by a bonding material 108 such as solder. A second lead frame 106 is connected to the bottom surface of the semiconductor chip 102 by a bonding material 110. These elements are sealed altogether by a resin 112 such as epoxy or silicone.
As shown in FIG. 12, outer lead portions of lead frames 104, 106 extend from the bottom surface of the semiconductor device to be connected to a mounting substrate not shown.
In case of this structure, thickness T of the package is the total thickness of those and other elements, namely, (upper resin layer 112A)+(first lead frame 104)+(bonding material 108)+semiconductor chip 102)+(bonding material 110)+(second lead frame 106)+(lower resin layer 112B). Therefore, there is a limit for thinning the thickness T of the package.
In addition, since the lower surface of the second lead frame 106 is covered by the resin layer 112B that is relatively low in heat conductivity, capability of dissipating heat generated from the semiconductor chip 102 during powered operation is inevitably limitative.
According to an embodiment of the invention, there is provided a semiconductor device of a surface-mounting type having a mount surface to be joined with a mounting substrate, comprising: a semiconductor chip having a bottom surface, a top surface, a heat-generating portion located nearer to said top surface than said bottom surface and generating heat during operation, and at least one patterned electrode formed on said top surface; a resin provided to cover said semiconductor chip; and an electrode terminal extracted from said bottom surface of said semiconductor chip, a mounting face of an electrode terminal and a surface of said patterned electrode being exposed on said mount surface to be substantially flush with a plane of said mount surface, and a perimeter of said patterned electrode being surrounded by said resin on said mount surface.
According to another embodiment of the invention, there is provided a semiconductor device of a surface-mounting type having a mount surface to be joined with a mounting substrate, comprising: a lead frame; a semiconductor chip bonded said lead frame, and having at least one electrode smaller than said semiconductor chip; and a resin provided to cover said semiconductor chip, a mounting face of said lead frame and a surface of the electrode being exposed on said mount surface to be flush with a plane of said mount surface, and a perimeter of said electrode being surrounded by said resin on said mount surface.
According to yet another embodiment of the invention, there is provided a semiconductor device comprising: a lead frame having a bonding portion and an electrode terminal; a semiconductor chip having a top surface, a bottom surface, and at least one patterned electrode formed on said top surface, said bottom surface being bonded to said bonding portion of said lead frame; and a resin provided to cover said semiconductor chip, a mounting face of said electrode terminal of said lead frame being provided to be substantially flush with a surface of said patterned electrode, the surface of said patterned electrode being exposed to said top surface of said semiconductor chip, and a perimeter of said surface of said patterned electrode being covered by said resin.